Computational Time, Latency, Throughput Improvement Using Tabulation Method Multiplier

Vinay Patel; Vinod Pathak

Multiplier operation is depends on the speed of adder. Speed of adder is affected to its path propagation delay. Thus the multiplier is usually slowest and area consuming element in the system. Our designs offer tradeoffs between Computational time area, latency and throughput for performing multiplication. Our designs offer tradeoffs between Computational time area, latency and throughput for performing multiplication. A fast computation of multiplication operations of two finite length sequences implemented with the help of this propose algorithm is possible using VHDL language. A parallel architecture for multiplication using tabulation method is design for this purpose. Since it gives faster addition in multiplication process with less number of transistor. The carries of this adder are computed in parallel by two independent 4-bit carry chains which reduces the carry chain length. The circuit is propose for 8-bit adder module with significant operating speed improvement compared to the corresponding adders.

Select Volume / Issues:

• Volume 7,Issue 2, Mar. 2016

Year:

2016

Type of Publication:

Article

Keywords:

Redundant; Tabulation Method; Partial Product; Area Delay Product ADP

Journal:

IJECCE

Volume:

7

Number:

2

Pages:

109-112

Month:

March

ISSN:

2249-071X