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Volume 4 Issue 5, Sept. 2013

Description

Publications

• Reddy, N. Amarnath and D. Srinivasa Rao. "Design and Simulation of Pipelined FFT Processor Using FPGA". IJECCE 4.5 (2013): 1361-1365. [More] 
• Rastogi, Mansi and Rajesh Mehra. "Design and Simulation of Turbo Codec for Error Reduction Using MSOVA Algorithm". IJECCE 4.5 (2013): 1535-1540. [More] 
• Nagendra, B. R. et al. "Design of Ingenious Randlet, Sinelet and Shocklets for Compression of Satellites Vibration Test Data". IJECCE 4.5 (2013): 1341-1348. [More] 
• Prakash, Vemula, Mekala Rama Rao and Dr. M. Ch. P. Jagdissh. "Design of Low Power Column Bypass Multiplier using FPGA and Implementation Using FIR Filter". IJECCE 4.5 (2013): 1571-1574. [More] 
• Garg, Honey, Namit Gupta and Chintan Patel. "Design of Wireless Sensor Node for Agriculture Field Monitoring". IJECCE 4.5 (2013): 1524-1526. [More]